1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device having reduced number of pins used for testing.
2. Description of Related Art
In response to a write command applied from a tester, a conventional semiconductor device writes data to a memory cell. Then, in response to a read command from the memory cell, the semiconductor device reads the data. The memory cell is considered as normal when write data is the same as read data and is considered as abnormal when write data is different from read data.
When the test is performed by the method described above, there is a limited number of semiconductor memory devices which can be tested in parallel. For example, if the number of input/output (I/O) pins (or pads) of the tester is sixty four (64) and the number of data I/O pins of the semiconductor memory device to be tested is eight, then only eight semiconductor memory devices can be tested because one semiconductor memory device occupies eight I/O pins of the tester. More details are explained below with reference to FIG. 1.
To increase the number of semiconductor memory devices that can be tested in parallel, a parallel bit test technique has been proposed. The parallel bit test technique includes an additional circuit in a semiconductor chip and receives or outputs data not through all data I/O pins but through a predetermined number of data I/O pins. Data inputted through a predetermined number of data I/O pins are multiplexed by the additional circuit in the semiconductor chip, and the multiplexed data is written to a memory cell. Comparison result signals are generated by comparing two bits of data outputted from the memory cell. The comparison result signals are outputted through a predetermined number of data I/O pins.
Even though the parallel bit test may increase the number of the semiconductor memory devices to be tested, test results can be unreliable because the comparison result signal is generated by comparing data by two bits. A comparison result may indicate that the memory cell is normal even if the compared 2-bit data are abnormal. More details are explained below with reference to FIG. 2.
A need therefore exists for a semiconductor memory device which reduces the number of pins used for a test and has a high reliability on the test.